The invention relates to a field-effect transistor containing, in a semiconductor layer, a doped channel region, two terminal regions, which are also referred to as drain and source, respectively, a control region, which is also referred to as gate, and an electrical insulating region between the control region and the channel region.
The semiconductor layer comprises a material having an electrical resistivity of between 10−4 Ω/cm to 108 Ω/cm (ohms per centimeter), for example silicon or gallium arsenide. The semiconductor layer is, by way of example, a semiconductor substrate with an n-type doping or p-type doping. However, there are also technologies in which the semiconductor layer has been applied on an insulating substrate, e.g. in accordance with SOI technology (Silicon On Insulator).
Field-effect transistors are differentiated into n-channel transistors and p-channel transistors depending on the type of channel which forms in the channel region.
A multiplicity of field-effect transistors are arranged in an integrated circuit arrangement, so that even small improvements or alterations to the construction of a field-effect transistor can lead to considerable improvement and increases in yield.
It is an object of the invention to specify a field-effect transistor of simple construction which, in particular, can be fabricated in a simple manner and which, in particular, can be fabricated with a small area requirement relative to the surface of the semiconductor wafer to be processed. Moreover, the intention is to specify an associated use and an associated fabrication method.
The field-effect transistor according to the invention contains a depression in the semiconductor layer, the control region and the electrical insulating region being arranged in said depression. The channel region runs along the depression in the semiconductor layer. The depression has an opening in a surface of the semiconductor layer that is to be processed, one terminal region lying in the vicinity of said opening. The other terminal region is further away from the opening than the terminal region near the opening and is therefore referred to as terminal region remote from the opening. The terminal region remote from the opening lies at the end of the depression, for example. In the field-effect transistor according to the invention, the terminal region remote from the opening leads from the interior of the semiconductor layer as far as a surface of the semiconductor layer that contains the opening, or is electrically conductively connected to an electrically conductive connection which leads to the surface.
The field-effect transistor according to the invention is thus a field-effect transistor whose channel region extends in the vertical direction with respect to the surface of the semiconductor layer or at least transversely with respect to said surface. As a result, the area required for the field-effect transistor becomes independent of the channel length required or becomes dependent given an inclined position of the channel region only over a factor of less than 1. In comparison with a planar field-effect transistor, however, the integration of the transistor into an integrated electrical circuit is not more complex because the terminal region remote from the opening, which region lies in the interior of the semiconductor layer, leads to the surface to be processed or is electrically conductively connected to said surface via an electrically conductive connection.
In one development of the field-effect transistor according to the invention, the two terminal regions have the same dopant concentration and dopants of the same conduction type, i.e. either n-conducting or p-conducting. In one refinement, the channel region has a doping of the opposite conduction type to the terminal regions and adjoins both terminal regions. Additional doping regions between the terminal regions are not present in this refinement.
In a next refinement, the channel region has a length corresponding to at least two thirds of the depth of the depression. In this development, the depression is introduced only to the depth necessary for obtaining the required channel length.
In another development, the depression is a trench. The length of the trench determines the transistor width, i.e. a critical parameter of the field-effect transistor. In an alternative development, the depression is a hole having a depth which exceeds the diameter or the width of the hole by at least two-fold, by way of example. The diameter of the hole determines the transistor width. The depth determines the gate length. In the case of cylindrical holes, in particular, layers can be deposited very uniformly on the hole wall.
In a next development of according to the invention, the field-effect transistor the channel region lies on both sides of the trench or along the entire periphery of the hole. By virtue of these measures, transistors having a comparatively large transistor width can also be fabricated in a simple manner.
In an alternative development, on the other hand, the channel region lies only on one side of the trench or only along part of the periphery of the hole. Transistors which require only a comparatively small width can thus be fabricated in a simple manner. Those regions at the trench or at the periphery of the hole which are not occupied by the channel region are utilized for the arrangement of other components or as part of insulating regions.
In a next development of the method according to the invention, the terminal region remote from the opening extends in the region of a plurality of depressions in which control regions are arranged. By way of example, the field-effect transistor contains two, three or more depressions lined up in the manner of a cascade. The cascading leads to a further reduction of the area requirement. Moreover, the terminal region remote from the opening only has to be led to the surface once per field-effect transistor, independently of the number of cascadings.
In a next development, the depression for the control region and a depression filled with an electrical insulating material between the field-effect transistor and an adjacent electrical component have the same depth. The two depressions can thus be fabricated in a simple manner in a common lithography process.
In an alternative development, by contrast, the depression for the control region has a smaller depth than a depression completely filled with an electrical insulating material between the field-effect transistor and an adjacent electronic component. This measure allows the depression for the insulating material to be made narrower without impairing the insulating capability in comparison with a wider insulation which, however, is not as deep.
In a next development, the individual elements of the field-effect transistor have dimensions and/or a structure which permit the switching of voltages of greater than 9 volts, greater than 15 volts, but less than 30 volts:                the insulating region has, by way of example, an insulating thickness of at least 15 run (nanometers) or of at least 20 nm,        the distance between the terminal regions along the depression is at least 0.4 μm (micrometer),        the terminal regions have a shallow doping profile gradient of about 200 run/decade in comparison with the doping profiles of planar field-effect transistors. In particular, the shallow doping profile gradient can be produced in a simple manner on account of different penetration depths of the dopants.        
The measures mentioned make it possible to produce field-effect transistors which only need less than half the area requirement in comparison with planar field-effect transistors with the same electrical properties. The area saving is particularly large in the aforementioned range of switching voltages and significantly outweighs the fabrication outlay for fabricating the depression.
The invention additionally relates to a use of the field-effect transistor, in particular the field-effect transistor for the aforementioned switching voltages, as driving transistor at a word line or a bit line of a memory cell array. The aforementioned switching voltages are required, in particular, for erasing but also for programming nonvolatile memory cells, such as e.g. of so-called flash memories, in which only a plurality of cells can be erased simultaneously, or of EEPROMs (Electrically Erasable Programmable Read-Only Memories).
In particular, the field-effect transistors according to the invention are used with a degree of integration of the memory cell array in the case of which the memory cell array would take up less than 30% of the chip area of a memory unit with the use of planar field-effect transistors for the driving.
The invention additionally relates simple fabrication method for field-effect transistor according to which:                a semiconductor layer having a surface to be processed is provided,        a terminal region near the surface and a terminal region remote from the surface are introduced into the semiconductor layer by doping,        at least one depression is etched for a control region from the terminal region near the surface as far as the terminal region remote from the surface,        an electrical insulating layer is deposited in the depression, and        an electrically conductive control introduced into the depression.        
In one development of the method according to the invention, the doping of the terminal regions is performed before the etching and the filling of the depressions, thus resulting in simple processing.
In a next development, a connecting region leading from the terminal region remote from the surface to the surface is doped. An electrically conductive connection is produced in the semiconductor layer a n a simple manner by means of the doping.
In another development, insulating depressions, so-called insulating trenches, are etched at the same time as the depression for the control region. In one refinement, the insulating depressions have the same depth as the depression for the control region. In an alternative, the insulating depressions are deeper than the depression for the control region.
In order to fabricate the insulating depression, in one development, a lithography method is performed in addition to the lithography method for fabricating the depression for the control region. In the additional lithography method, the insulating depressions are etched either to their entire depth or to the depth in which they exceed the depth of the depression for the control region.
In another development with depressions of different depths, however, the depressions are etched by means of a common etching process in which wider depressions are etched considerably more deeply than narrower depressions.